This invention relates to a nonvolatile semiconductor memory device. More particularly, this invention relates to, for example, a NAND flash memory capable of reading data from a negative threshold cell.
In a nonvolatile semiconductor memory device, such as a NAND flash memory, a high electric field is applied to trap electrons in an oxide film. In this situation, data is written by changing the threshold value of a memory cell. Moreover, data is read by making use of the difference in threshold value between cells. This holds true for a multilevel semiconductor memory device (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2001-332093).
Here, the read operation of a conventional NAND flash memory of the shielded bit line type will be explained briefly.
First, the source line and well of a cell are set to ground potential VSS (0V) and a potential VSG (V=VDD+Vth) is applied to the gate (BLPRE) of an n-type MOS transistor in a sense amplifier. The potential VSG is a voltage of about 4V at which the n-type MOS transistor transfers an operating voltage VDD (2.5V). Then, a potential of 0.7V+Vth is applied to the gate (BLCLAMP) of an n-type MOS transistor which connects the sense amplifier to a bit line. This causes a voltage of 0.7V to be precharged on the bit line of the cell. Vth is the threshold voltage of the corresponding transistor.
All of the bit lines are not precharged to 0.7V. The bit lines are precharged to 0.7V, 0V, 0.7V, 0V, . . . , alternately, which makes the number of bit lines used in reading (or selected bit lines) half of the total number of bit lines. That is, in a read operation, an amplitude develops on a bit line, depending on the data. The adjacent bit lines are influenced by the capacitive coupling of the amplitude. Therefore, to prevent the data in the adjacent cells from causing data corruption, the select bit lines used for reading are shielded.
After the precharging, the potential of the gate (BLCLAMP) of the n-type MOS transistor is set at zero, thereby disconnecting the bit line from the sense amplifier. Moreover, a desired potential VCGRV is applied to the word line of the cell to be read from. A potential VREAD (about 5V) which never fails to turn on the transistor is applied to the remaining word lines and drain-side select gate lines. Lastly, the potential VREAD is applied to the source-side select gate line. This causes a cell current to flow if the cell to be read from is on, with the result that the voltage of the bit line approaches zero. If the cell is off, no cell current flows, causing the bit line to remain at the precharge potential (0.7V).
The voltage of the gate (BLPRE) of the n-type MOS transistor is raised again. Then, a node (TDC) connected to the latch circuit of the sense amplifier is precharged to the operating voltage VDD. Thereafter, the gate (BLCLAMP) of the n-type MOS transistor is set to a potential VSEN (=0.35V+Vth).
The capacitance of the node (TDC) is lower than that of the bit line. Therefore, when the cell is on, if the voltage of the bit line is lower than 0.35V, charge sharing is done. That is, the voltage at the node (TDC) becomes equal to the voltage of the bit line. On the other hand, in a case where the cell is off, if the voltage of the bit line is 0.7V, the n-type MOS transistor on the gate (BLCLAMP) side cannot exceed the threshold value, with the result that the transistor remains off. That is, the voltage at the node (TDC) remains at the operating voltage VDD. In this way, raising the voltage of the gate (BLPRE) of the n-type MOS transistor between the latch circuit and the node (TDC) causes the voltage at the node (TDC) to be transferred to the latch circuit, thereby determining whether the data is high or low.
Changing the voltage VCGRV of the word line of the cell to be read from makes it possible to identify the threshold value of the cell. For example, if the cell has two threshold values, this means that it is possible to identify 2-value data. If the cell has four threshold values, this means that it is possible to identify 4-value data.
Here, if the cell has 16 threshold values, this means that it is possible to identify 16-value data. To be possible to identify 16-value data, however, the retention margin for each threshold value is curtailed. If the distribution of the threshold value is set on the more positive side (higher side), the retention margin can be secured. However, if the distribution of the threshold value is set on the too high side, the write voltage and read voltage also increase accordingly. For this reason, read and write operations are liable to be affected by disturbance as a result of rises in the write and read voltages. Increased disturbance may cause the shift of the set threshold value. A shift in the threshold value is a factor that causes erroneous reading.
To overcome this problem, the following method can be considered: setting the threshold value of the cell on the negative side enables the retention margin to be improved without increasing disturbance in read and write operations.
A method of realizing this is to apply a negative potential to the word line itself. To achieve this, the configuration of the well has to be changed, leading to the demerit of increasing the number of processes during manufacture.
Furthermore, another method is to be capable of setting the threshold value VGS of an actual cell (cell word line voltage-cell source line voltage) to a negative value in a case where only a positive voltage is applied to the word line by applying a bias to the source line and p-well of the cell. That is, it is possible to form the distribution of threshold values of the cell also on the negative side.
In this method, however, the bias is applied to the source line and p-well of the cell which require no precharging. Then, the consumption current increases. Moreover, the read time and write time (the write time including a verify operation such as a read operation after writing) increase by the time required to precharge the source line and p-well of the cell.
Specifically, when no bias is applied to the source line and p-well of the cell, the amount of charge necessary for the operation is the charge amount needed to precharge the bit line. When a bias is applied to the source line and p-well of the cell, not only the charge amount needed to bias the source and p-well of the cell, and the unselected bit lines (shielded bit lines) but also the charge amount needed to precharge the bit line are required.
In addition to the NAND flash memory of the shielded bit line type, another conventional NAND flash memory is such that a read operation is performed on all of the bit lines simultaneously (in the all-bit-line select sense method) (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2006-85839).
In the case of the all-bit-line select sense method, too, since the distribution of threshold values of the cell is also formed on the negative side, a bias is applied to the source lines and p-wells of the cells in not only the selected block but also the unselected blocks. In this case, the current (charge amount) needed to precharge the bit line increases as compared with a case where no bias is applied. Therefore, as in the shielded bit line type, the consumption current may increase.
Furthermore, as in the shielded bit line type, the read time and write time (the write time including a verify operation such as a read operation after writing) increase by the time required to precharge the source line and p-well of the cell.
In short, when a bias is applied so that the source line and p-well of the cell are biased to a positive voltage (e.g., 1V) (the voltage of the selected word line is set to about zero) to read a negative threshold cell, the current consumption increases and so it takes longer to perform read and write operations.